ADSP-21161NKCAZ100

ANALOG DEVICES  ADSP-21161NKCAZ100  芯片, 数字信号处理器, 控制器, 32位, 225MBGA

The is a high performance Digital Signal Processor featuring Analog Devices" super Harvard architecture SHARC. Easing portability, the ADSP-21161N is source code compatible with the ADSP-21160 and with first generation ADSP-2106x SHARC processors in SISD single-instruction, single-data mode. Like other SHARC DSPs, the ADSP-21161N is a 32-bit processor that is optimized for high performance DSP applications. The ADSP-21161N offers a single-instruction multiple-data SIMD architecture. Using two computational units ADSP-2106x SHARC processors have one, the ADSP-21161N can double cycle performance versus the ADSP-2106x on a range of DSP algorithms. Fabricated in a state of the art, high speed, low power CMOS process, the ADSP-21161N has a 10 or 9ns instruction cycle time. With its SIMD computational hardware running at 110MHz, the ADSP-21161N can perform 660 million floating point operations per second.

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Super Harvard architecture SHARC processor

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Code compatible with all other SHARC family DSPs

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Supports 32-bit fixed, 32-bit float and 40-bit floating-point formats

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Single-cycle instruction execution, including SIMD operations in both computational units

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Four independent buses for dual data fetch, instruction fetch and nonintrusive zero overhead I/O