DDR DRAM, 128MX16, 0.4ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84
* High speed data transferrates with system frequency up to 400 MHz - 8 internal banks for concurrent operation - 4-bit prefetch architecture - Programmable CAS Latency: 3, 4 ,5 , 6 and 7 - Programmable Additive Latency: 0, 1, 2, 3 , 4, 5 and 6 - Write Latency = Read Latency -1 - Programmable Wrap Sequence: Sequential or Interleave - Programmable Burst Length: 4 and 8 - Automatic and Controlled Precharge Command - Power Down Mode - Auto Refresh and Self Refresh - Refresh Interval:7.8 us8192 cycles/64ms Tcase between 0°C and 85°C - ODT On-Die Termination - Weak Strength Data-Output Driver Option - Bidirectional differential Data Strobe Single-ended data-strobe is an optional feature - On-Chip DLL aligns DQ and DQs transitions with CK transitions - DQS can be disabled forsingle-ended data strobe - Differential clock inputs CK and CK - JEDEC Power Supply 1.8V ± 0.1V - VDDQ =1.8V ± 0.1V - Available in 84-ball FBGA - RoHS compliant - PASR Partial Array Self Refresh - tRAS lockoutsupported