AT91SAM9G15-CU

AT91 系列 400 MHz 64 kB 闪存 32 kB SRAM 16/32 位 微控制器 - BGA-217

The is a SMART 400MHz 32-bit Embedded Microprocessor unit based on ARM926EJ-S processor. This MPU integrates a rich set of peripherals to support embedded industrial applications that require advanced user interfaces and high-speed communication. The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D acceleration and a 10-bit ADC that supports 4-wire/5-wire resistive touchscreen panels. Multiple communication interfaces include a soft modem supporting exclusively the Conexant SmartDAA line driver, HS USB Host and Device and FS USB Host with dedicated on-chip transceivers, two HS SDCard/SDIO/MMC interfaces, USARTs, SPIs, I²S and TWIs. The 10-layer bus matrix coupled with multiple DMA channels ensures uninterrupted data transfers with minimal processor overhead. The external bus interface incorporates controllers for 4-bank and 8-bank DDR2/LPDDR, SDRAM/LPSDRAM, static memories.

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ARM926EJ-S ARM Thumb processor running at up to 400MHz at 1.0V ± 10%

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16kB Data cache, 16kB Instruction cache, memory management unit

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System running at up to 133MHz

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Power-on reset cells, reset controller, shutdown controller, periodic interval timer, WDT and RTC

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Internal low power 32kHz RC and fast 12MHz RC oscillators

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Selectable 32768Hz low-power oscillator and 12MHz oscillator

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One PLL for the system and one PLL at 480MHz optimized for USB high speed

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Twelve 32-bit-layer AHB bus matrix for large bandwidth transfers

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Dual peripheral bridge with dedicated programmable clock for best performances

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Two dual port 8-channel DMA controllers DMAC

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Advanced interrupt controller AIC and debug unit DBGU

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Two programmable external clock signals

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Shutdown controller with four 32-bit battery backup registers

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Clock generator and power management controller

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Very slow clock operating mode, software programmable power optimization capabilities

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Four 32-bit parallel I/O controllers

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105 Programmable I/O lines multiplexed with up to three peripheral I/Os

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Input change interrupt capability on each I/O line, optional Schmitt trigger input

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Individually programmable open-drain, pull-up and pull-down resistor, synchronous output

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One 64kB internal ROM embedding bootstrap routine