AD9574BCPZ

ANALOG DEVICES  AD9574BCPZ  芯片, 以太网, 时钟发生器, 312.5MHZ, LFCSP

Product Details

The AD9574 provides a multiple output clock generator function comprising a dedicated phase-locked loop PLL core optimized for Ethernet and gigabit Ethernet line card applications. The integer-N PLL design is based on the Analog Devices, Inc., proven portfolio of high performance, low jitter frequency synthesizers to maximize network performance. The AD9574 also benefits other applications requiring low phase noise and jitter performance.

Configuring the AD9574 for a particular application requires only the connection of external pull-up or pull-down resistors to the appropriate pin program reader pins PPRx. These pins provide control of the internal dividers for establishing the desired frequency translations, clock output functionality, and input reference functionality. Connecting an external 19.44 MHz or 25 MHz oscillator to one or both of the REF0_P/REF0_N or REF1_P/REF1_N reference inputs results in a set of output frequencies prescribed by the PPRx pins. Connecting a stable clock source 8 kHz/10 MHz/19.44 MHz/25 MHz/38.88 MHz to the monitor clock input enables the optional monitor circuit providing quality of service QoS status for REF0 or REF1.

The PLL section consists of a low noise phase frequency detector PFD, a precision charge pump CP, a partially integrated loop filter LF, a low phase noise voltage controlled oscillator VCO, and feedback and output dividers. The divider values depend on the PPRx pins. The integrated loop filter requires only a single external capacitor connected to the LF pin.

The AD9574 is packaged in a 48-lead 7 mm × 7 mm LFCSP, requiring only a single 3.3 V supply. The operating temperature range is −40°C to +85°C.

**Applications**

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Ethernet line cards, switches, and routers

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SATA and PCI express

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Low jitter, low phase noise clock generation

### Features and Benefits

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Redundant input reference clock capability

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Reference monitoring function

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Fully integrated VCO/PLL core

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Jitter rms

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0.234 ps rms jitter 10 kHz to 10 MHz at 156.25 MHz

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0.243 ps rms jitter 12 kHz to 20 MHz at 156.25 MHz

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Input frequency: 19.44 MHz or 25 MHz

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Preset frequency translations

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Using a 19.44 MHz input reference

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19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz

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Using a 25 MHz input reference

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25 MHz, 33.33 MHz, 50 MHz, 66.67 MHz, 80 MHz, 100 MHz, 125 MHz, 133.3 MHz, 156.25 MHz, 160 MHz, 312.5 MHz

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Output drive formats: HSTL, LVDS, HCSL, and 1.8 V and 3.3 V CMOS

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Integrated loop filter requires a single external capacitor

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2 copies of reference clock output

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Device configuration via strapping pins PPRx

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Space-saving 7 mm × 7 mm 48-lead LFCSP

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3.3 V operation