ADN2811ACPZ-CML

PLL Clock Generator Single 48Pin LFCSP EP

Product Details

The ADN2811 provides the receiver functions of quantization, signal level detect, and clock and data recovery at OC-48 and OC-48 FEC rates. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted.

The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip oscillator with external crystal. Both the 2.48 Gbps and 2.66 Gbps digital wrapper rates are supported by the ADN2811, without any change of reference clock.

This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power, fiber optic receiver.

The receiver front end signal detect circuit indicates when the input signal level has fallen below a user-adjustable threshold. The signal detect circuit has hysteresis to prevent chatter at the output.

The ADN2811 is available in a compact, 7 mm × 7 mm, 48-lead chip scale package.

Applications

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SONET OC-48, SDH STM-16, and 15/14 FEC

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WDM transponders

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Regenerators/repeaters

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Test equipment

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Backplane applications

### Features and Benefits

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Meets SONET requirements for jitter transfer/generation/tolerance

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Quantizer sensitivity: 4 mV typical

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Adjustable slice level: ±100 mV

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1.9 GHz minimum bandwidth

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Patented clock recovery architecture

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Loss of signal detect range: 3 mV to 15 mV

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Single reference clock frequency for both native SONET and 15/14 7% wrapper rate

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Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK

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LVPECL/LVDS/LVCMOS/LVTTL compatible inputs LVPECL/LVDS only at 155.52 MHz

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19.44 MHz on-chip oscillator to be used with external crystal

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Loss of lock indicator

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Loopback mode for high speed test data

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Output squelch and bypass features

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Single-supply operation: 3.3 V

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Low power: 540 mW typical

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7 mm × 7 mm, 48-lead LFCSP