光纤接收器与量化器和时钟恢复和数据重定时 Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
Product Details
The AD807 provides the receiver functions of data quantization, signal level detect, clock recovery and data retiming for 155 Mbps NRZ data. The device, together with a PIN diode/preamplifier combination, can be used for a highly integrated, low cost, low power SONET OC-3 or SDH STM-1 fiber optic receiver.
The receiver front end signal level detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor. The signal level detect circuit 3 dB optical hysteresis prevents chatter at the signal level detect output.
The PLL has a factory trimmed VCO center frequency and a frequency acquisition control loop that combine to guarantee frequency acquisition without false lock. This eliminates a reliance on external components such as a crystal or a SAW filter, to aid frequency acquisition.
The AD807 acquires frequency and phase lock on input data using two control loops that work without requiring external control. The frequency acquisition control loop initially acquires the frequency of the input data, acquiring frequency lock on random or scrambled data without the need for a preamble. At frequency lock, the frequency error is zero and the frequency detector has no further effect. The phase acquisition control loop then works to ensure that the output phase tracks the input phase. A patented phase detector has virtually eliminated pattern jitter throughout the AD807.
The device VCO uses a ring oscillator architecture and patented low noise design techniques. Jitter is 2.0 degrees rms. This low jitter results from using a fully differential signal architecture, Power Supply Rejection Ratio circuitry and a dielectrically isolated process that provides immunity from extraneous signals on the IC. The device can withstand hundreds of millivolts of power supply noise without an effect on jitter performance.
The user sets the jitter peaking and acquisition time of the PLL by choosing a damping factor capacitor whose value determines loop damping. CCITT G.958 Type A jitter transfer requirements can easily be met with a damping factor of 5 or greater.
Device design guarantees that the clock output frequency will drift by less than 20% in the absence of input data transitions. Shorting the damping factor capacitor, CD, brings the clock output frequency to the VCO center frequency.
The AD807 consumes 140 mW and operates from a single power supply at either +5 V or –5.2 V.
### Features and Benefits
频率 155.52 MHz
电源电压DC 5.50V max
输出接口数 5
供电电流 39.5 mA
耗散功率 170 mW
数据速率 155 Mbps
上升时间 1.5 ns
下降时间Max 1.5 ns
工作温度Max 85 ℃
工作温度Min -40 ℃
耗散功率Max 170 mW
电源电压 4.5V ~ 5.5V
电源电压Max 5.5 V
电源电压Min 4.5 V
安装方式 Surface Mount
引脚数 16
封装 SOIC-16
高度 1.5 mm
封装 SOIC-16
工作温度 -40℃ ~ 85℃
产品生命周期 Active
包装方式 Tube
RoHS标准 Non-Compliant
含铅标准 Contains Lead
REACH SVHC标准 No SVHC
REACH SVHC版本 2015/12/17
香港进出口证 NLR
型号/品牌 | 代替类型 | 替代型号对比 |
---|---|---|
AD807A-155BR ADI 亚德诺 | 当前型号 | 当前型号 |
AD807A-155BRZ 亚德诺 | 类似代替 | AD807A-155BR和AD807A-155BRZ的区别 |
AD807A-155BRZRL7 亚德诺 | 功能相似 | AD807A-155BR和AD807A-155BRZRL7的区别 |