ATF1504ASVL-20JU44

CPLD, 64 MACROCELL, w/ ISP, LOW POWER, 3.3V - 20NS, 44 PLCC, IND TEMP, GREEN

**Description**

The ATF1504ASVL is a high-performance, high-density complex programmable logic device CPLD that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic acrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504ASVL’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications.

**Features**

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*High-density, High-performance, Electrically-erasable Complex ****Programmable Logic Device**

**– 3.0 to 3.6V Operating Range**

**– 64 Macrocells**

**– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell**

**– 44, 68, 84, 100 Pins**

**– 15 ns Maximum Pin-to-pin Delay**

**– Registered Operation up to 77 MHz**

**– Enhanced Routing Resources**

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*In-System Programmability ISP via JTAG**

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*Flexible Logic Macrocell**

**– D/T/Latch Configurable Flip-flops**

**– Global and Individual Register Control Signals**

**– Global and Individual Output Enable**

**– Programmable Output Slew Rate**

**– Programmable Output Open-collector Option**

**– Maximum Logic Utilization by Burying a Register with a COM Output**

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*Advanced Power Management Features**

**– Automatic 5 µA Standby for “L” Version**

**– Pin-controlled 100 µA Standby Mode Typical**

**– Programmable Pin-keeper Circuits on Inputs and I/Os**

**– Reduced-power Feature per Macrocell**

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*Available in Commercial and Industrial Temperature Ranges**

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*Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP**

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*Advanced EE Technology**

**– 100% Tested**

**– Completely Reprogrammable**

**– 10,000 Program/Erase Cycles**

**– 20 Year Data Retention**

**– 2000V ESD Protection**

**– 200 mA Latch-up Immunity**

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*JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported**

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*PCI-compliant**

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*Security Fuse Feature**

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*Green Pb/Halide-free/RoHS Compliant Package Options**

**Enhanced Features**

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*Improved Connectivity Additional Feedback Routing, Alternate Input Routing**

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*Output Enable Product Terms**

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*Transparent-latch Mode**

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*Combinatorial Output with Registered Feedback within Any Macrocell**

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*Three Global Clock Pins**

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*ITD Input Transition Detection Circuits on Global Clocks, Inputs and I/O**

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*Fast Registered Input from Product Term**

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*Programmable “Pin-keeper” Option**

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*V****CC ****Power-up Reset Option**

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*Pull-up Option on JTAG Pins TMS and TDI**

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*Advanced Power Management Features**

**– Edge-controlled Power-down “L”**

**– Individual Macrocell Power Option**

**– Disable ITD on Global Clocks, Inputs and I/O**