ADC Dual Pipelined 1GSPS 14Bit Serial 64Pin LFCSP EP T/R
JESD204B Subclass 1 coded serial digital outputs 1.65 W total power per channel at 1 GSPS default settings SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR at 1 GSPS = 65.3 dBFS at 340 MHz AIN = −1.0 dBFS, 60.5 dBFS at 1 GHz AIN = −1.0 dBFS ENOB = 10.8 bits at 10 MHz DNL = ±0.5 LSB INL = ±2.5 LSB Noise density = −154 dBFS/Hz at 1 GSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation No missing codes Internal ADC voltage reference Flexible input range: 1.46 V p-p to 1.94 V p-p AD9680-1250: 1.58 V p-p nominal AD9680-1000 and AD9680-820: 1.70 V p-p nominal AD9680-500: 1.46 V p-p to 2.06 V p-p 2.06 V p-p nominal Programmable termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 half-band filters Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither
