ADSP-2181KSTZ-115

DSP Fixed-Point 16Bit 28.8MHz 28.8MIPS 128Pin LQFP

* 25 ns Instruction Cycle Time from 20 MHz Crystal@ 5.0 Volts * 40 MIPS Sustained Performance * Single-Cycle Instruction Execution * Single-Cycle Context Switch * 3-Bus Architecture Allows Dual Operand Fetches inEvery Instruction Cycle * Multifunction Instructions * Power-Down Mode Featuring Low CMOS Standby * Power Dissipation with 100 Cycle Recovery from * Power-Down Condition * Low Power Dissipation in Idle Mode * INTEGRATION * ADSP-2100 Family Code Compatible, with InstructionSet Extensions * 80K Bytes of On-Chip RAM, Configured as * 16K Words On-Chip Program Memory RAM * 16K Words On-Chip Data Memory RAM * Dual Purpose Program Memory for Both Instructionand Data Storage * Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units * Two Independent Data Address Generators * Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution * Programmable 16-Bit Interval Timer with Prescaler128-Lead TQFP/128-Lead PQFP * SYSTEM INTERFACE * 16-Bit Internal DMA Port for High Speed Access toOn-Chip Memory * 4 MByte Memory Interface for Storage of Data Tablesand Program Overlays * 8-Bit DMA to Byte Memory for TransparentProgram and Data Memory Transfers * I/O Memory Interface with 2048 Locations SupportsParallel Peripherals * Programmable Memory Strobe and Separate I/O MemorySpace Permits “Glueless” System Design * Programmable Wait State Generation * Two Double-Buffered Serial Ports with CompandingHardware and Automatic Data Buffering * Automatic Booting of On-Chip Program Memory fromByte-Wide External Memory, e.g., EPROM, orThrough Internal DMA Port * Six External Interrupts * 13 Programmable Flag Pins Provide Flexible SystemSignaling * ICE-Port™ Emulator Interface Supports Debuggingin Final Systems