LTC6954IUFF-1#PBF

LINEAR TECHNOLOGY  LTC6954IUFF-1#PBF  芯片, 时钟分配器, 1.8GHZ, QFN-36

The is a low phase noise, triple output clock distribution divider/driver in 36 pin QFN package. It has three outputs and each output is individually programmable to divide the input frequency by any integer from 1 to 63 and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50% regardless of the divide number. It also features "s EZSync system for perfect clock synchronization and alignment every time. The device settings are controlled through an SPI-compatible serial port. It is used in clocking high speed, high resolution ADCs, DACs and data acquisition systems and low jitter clock distribution.

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Supply voltage range from 3.15V to 3.45V

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Maximum supply current is 350mA

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Three LVPECL low noise outputs

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Additive jitter<20fsRMS 12KHz to 20MHz, additive jitter< 85fsRMS 10Hz to nyquist

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Maximum input frequency is 1.8GHz when DELAY = 0

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Maximum input frequency is 1.4GHz when DELAY > 0

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Operating temperature range from -40°C to 105°C