LF398S8#PBF

LINEAR TECHNOLOGY  LF398S8#PBF  采样保持放大器, 1个放大器, 4 µs, 2 mV, SOIC, 8 引脚

The is a precision Sample and Hold Amplifier uses a combination of bipolar and junction FET transistors to provide precision, high speed and long hold times. A typical offset voltage of 2mV and gain error of 0.004% allows this sample and hold amplifier to be used in 12-bit systems. Dynamic performance can be optimized by proper selection of the external hold capacitor. Acquisition times can be as low as 4µs for small capacitors while hold step and droop errors can be held below 0.1mV and 30µV/sec respectively when using larger capacitors. It is fixed at unity gain with 10R input impedance independent of sample/hold mode. The logic inputs are high impedance differential to allow easy interfacing to any logic family without ground loop problems. A separate offset adjust pin can be used to zero the offset voltage in either the sample or hold mode. The hold capacitor can be driven with an external signal to provide precision level shifting or "differencing" operation.

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4µs Typical acquisition time

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Guaranteed 0.01% maximum gain error

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2mV Typical offset voltage

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2.5mV Maximum hold step

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Very low feed through 80dB minimum

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High input impedance under all conditions

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Logic inputs compatible with all logic families