LCMXO640C-3TN100C

LATTICE SEMICONDUCTOR  LCMXO640C-3TN100C  可编程逻辑芯片, PLD, 640查找表, MACHXO, 100TQFP

The MachXO series Complex Programmable Logic Device CPLD with low capacity FPGAs, features glue logic, bus bridging, bus interfacing, power-up control and control logic. These devices bring together the best features of CPLD and FPGA devices on a single chip. The devices use look-up tables LUTs and embedded block memories traditionally associated with FPGAs for flexible and efficient logic implementation. Through non-volatile technology, the devices provide the single-chip, high-security, instant-ON capabilities traditionally associated with CPLDs. Finally, advanced process technology and careful design will provide the high pin-to-pin performance also associated with CPLDs. The ispLEVER® design tools from Lattice allow complex designs to be efficiently implemented using the MachXO family of devices. Popular logic synthesis tools provide synthesis library support for MachXO.

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Non-volatile, infinitely reconfigurable

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Sleep mode

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TransFR™ reconfiguration TFR

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High I/O to logic density

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Embedded and distributed memory

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Flexible I/O buffer

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sysCLOCK™ PLLs

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System level support