5V ECL ÷2,÷4,÷8 时钟发生芯片
The MC10/100EL34 is a low skew divide by 2, divide by 4, divide by 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the V output, a sinusoidal source can be AC coupled into the device see Interfacing section of the ECLinPS Data Book DL140/D. If a single-ended input is to be used, the V output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The V output is designed to act as the switching reference for the input of the EL34 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. The common enable EN is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset MR input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system.The 100 Series contains temperature compensation.
Features
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型号/品牌 | 代替类型 | 替代型号对比 |
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MC10EL34DG ON Semiconductor 安森美 | 当前型号 | 当前型号 |
MC100EL34DR2G 安森美 | 完全替代 | MC10EL34DG和MC100EL34DR2G的区别 |
MC10EL34DR2G 安森美 | 完全替代 | MC10EL34DG和MC10EL34DR2G的区别 |
MC100EL34DG 安森美 | 类似代替 | MC10EL34DG和MC100EL34DG的区别 |