MC100LVEL34DR2G

3.3V ECL ÷2,÷4,÷8 时钟发生芯片

The MC100LVEL34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The common enable EN bar is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulsecould lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon start−up, the internal flip-flops will attain a random state; the master reset MR input allows for the synchronization of the internaldividers, as well as multiple LVEL34s in a system.

Features

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50 ps Typical Output-to-Output Skew

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Synchronous Enable/Disable

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Master Reset for Synchronization

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1.5 GHz Toggle Frequency

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The 100 Series Contains Temperature Compensation.

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PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0V

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NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V

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Open Input Default State

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LVDS Input Compatible

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Pb-Free Packages are Available