3.3V ECL 1 : 5时钟分配芯片 3.3V ECL 1:5 Clock Distribution Chip
The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of -3.0 V to -3.8 V or 3.0 V to 3.8 V. The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW or left open and pulled LOW by the input pulldown resistor the SEL pin will select the differential clock input. The common enable EN is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
Features
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with VEE = 0 V
with VEE = -3.0 V to -3.8 V
Oxygen Index 28 to 34
型号/品牌 | 代替类型 | 替代型号对比 |
---|---|---|
MC100LVEL14DWR2G ON Semiconductor 安森美 | 当前型号 | 当前型号 |
MC100LVEL14DWG 安森美 | 完全替代 | MC100LVEL14DWR2G和MC100LVEL14DWG的区别 |
MC100EP139DWG 安森美 | 类似代替 | MC100LVEL14DWR2G和MC100EP139DWG的区别 |
MC100EL14DWR2G 安森美 | 类似代替 | MC100LVEL14DWR2G和MC100EL14DWR2G的区别 |