MC100EP139DTR2G

MC100EP139DTR2G图片1
MC100EP139DTR2G图片2
MC100EP139DTR2G图片3
MC100EP139DTR2G图片4
MC100EP139DTR2G图片5
MC100EP139DTR2G图片6
MC100EP139DTR2G图片7
MC100EP139DTR2G图片8
MC100EP139DTR2G图片9
MC100EP139DTR2G概述

3.3V/5V ECL ÷·2/4,÷·4/5/6 时钟发生器

The MC10/100EP139 is a low skew divide by 2/4, divide by 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the V output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the V output should be connected to the CLKbar input and bypassed to ground via a 0.01uF capacitor.The common enable ENbar is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset MR input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the divide by 2/4 and the divide by 4/5/6 outputs of a single device. All V pins must be externally connected to power supply to guarantee proper operation.The 100 Series contains temperature compensation.

Features

---

 |

.
Maximum Frequency >1.0 GHz Typical
.
50ps Output-to-Output Skew
.
PECL Mode Operating Range: VCC=3.0 V to 5.5 V with VEE = 0 V
.
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
.
Open Input Default State
.
Safety Clamp on Inputs
.
Synchronous Enable/Disable
.
Master Reset for Synchronization of Multiple Chips
.
VBB Output
.
Pb-Free Packages are Available
MC100EP139DTR2G中文资料参数规格
技术参数

无卤素状态 Halogen Free

输出接口数 4

电路数 1

工作温度Max 85 ℃

工作温度Min -40 ℃

电源电压 3V ~ 5.5V

封装参数

安装方式 Surface Mount

引脚数 20

封装 TSSOP-20

外形尺寸

封装 TSSOP-20

物理参数

工作温度 -40℃ ~ 85℃

其他

产品生命周期 Active

包装方式 Tape & Reel TR

制造应用 Low-Clock Skew Generation

符合标准

RoHS标准 RoHS Compliant

含铅标准 Lead Free

海关信息

ECCN代码 EAR99

数据手册

MC100EP139DTR2G引脚图与封装图
MC100EP139DTR2G引脚图
MC100EP139DTR2G封装图
MC100EP139DTR2G封装焊盘图
在线购买MC100EP139DTR2G
型号: MC100EP139DTR2G
描述:3.3V/5V ECL ÷·2/4,÷·4/5/6 时钟发生器
替代型号MC100EP139DTR2G
型号/品牌 代替类型 替代型号对比

MC100EP139DTR2G

ON Semiconductor 安森美

当前型号

当前型号

MC100EP139DTG

安森美

完全替代

MC100EP139DTR2G和MC100EP139DTG的区别

MC100EP139DTR2

安森美

完全替代

MC100EP139DTR2G和MC100EP139DTR2的区别

ICS87339AGI-11

艾迪悌

功能相似

MC100EP139DTR2G和ICS87339AGI-11的区别

锐单商城 - 一站式电子元器件采购平台