3.3/5V ECL 单D触发器
The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V and the CLKbar input will be biased at V
Features
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型号/品牌 | 代替类型 | 替代型号对比 |
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MC100EP51MNR4G ON Semiconductor 安森美 | 当前型号 | 当前型号 |
MC100EP52MNR4G 安森美 | 完全替代 | MC100EP51MNR4G和MC100EP52MNR4G的区别 |
MC100EP31MNR4G 安森美 | 完全替代 | MC100EP51MNR4G和MC100EP31MNR4G的区别 |
MC100LVEL51MNR4G 安森美 | 类似代替 | MC100EP51MNR4G和MC100LVEL51MNR4G的区别 |