MC100EPT21DR2G

ON SEMICONDUCTOR  MC100EPT21DR2G  Voltage Level Translator, 2 Input, 1.4 ns, 3 V to 3.6 V, SOIC-8 新

The is a 3.3V differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator in 8 pin SOIC package. Because LVPECL positive ECL, LVDS, positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8 lead SOIC package makes MC100EPT21DR2G ideal for applications which require the translation of a clock or data signal. The VBB output allows this device to be cap coupled in either single ended or differential input mode. VBB output is tied to D input and D is driven for a non inverting buffer or VBB output is tied to the D input and D is driven for an inverting buffer when single ended cap coupled. VBB output is connected through a resistor to each input pin when cap coupled differentially. If used the VBB pin should be bypassed to VCC via a 0.01µF capacitor. It is used in precision clock translation applications.

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1.4ns typical propagation delay

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Maximum frequency of 350MHz at TA = 25°C

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LVPECL/LVDS/CML inputs, LVTTL/LVCMOS outputs

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24mA TTL outputs

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Operating range VCC from 3V to 3.6V with GND = 0V

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Temperature compensation and VBB output

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Power supply current of 17mA outputs set to HIGH and 21mA outputs set to LOW

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Duty cycle skew of 50% and part to part skew of 500ps at TA = 25°C

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Output rise/fall times 0.8V to 2V of 600ps

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Operating temperature range from -40°C to +85°C