MC10E451FNR2G

5V ECL 6位D寄存器差分数据和时钟 5V ECL 6−Bit D Register Differential Data and Clock

The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock CLK input. A HIGH on the Master Reset MR input resets all Q outputs to LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below V pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V The 100 Series contains temperature compensation.

Features

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Differential Inputs: Data and Clock

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VBB Output

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1100MHz Min. Toggle Frequency

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Asynchronous Master Reset

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PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

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NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V

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Internal Input Pulldown Resistors

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ESD Protection: > 2 kV HBM, > 200 V MM

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Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

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Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

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Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34

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Transistor Count = 348 devices

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Pb-Free Packages are Available