评估板手册高频SOIC 8 Evaluation Board Manual for High Frequency SOIC 8
Description
The MC10/100EP31 is a D flip−flop with set and reset. The device is pin and functionally equivalent to the EL31 and LVEL31 devices. With AC performance much faster than the EL31 and LVEL31 devices, the EP31 is ideal for applications requiring the fastest AC performance available. Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip−flop when CLK is low and is transferred to the slave, and thus the outputs, upon a positive transition of the CLK.
Features
The 100 Series contains temperature compensation.
•340 ps Typical Propagation Delay
•Maximum Frequency > 3 GHz Typical
•PECL Mode Operating Range:
VCC= 3.0 V to 5.5 V with VEE= 0 V
•NECL Mode Operating Range:
VCC= 0 V with VEE= −3.0 V to −5.5 V
•Open Input Default State
•Q Output Will Default LOW with Inputs Open or at VEE
•Pb−Free Packages are Available
型号/品牌 | 代替类型 | 替代型号对比 |
---|---|---|
MC10EP31D ON Semiconductor 安森美 | 当前型号 | 当前型号 |
MC100EP31D 安森美 | 完全替代 | MC10EP31D和MC100EP31D的区别 |
MC100EP31DG 安森美 | 类似代替 | MC10EP31D和MC100EP31DG的区别 |
MC10EP35DG 安森美 | 类似代替 | MC10EP31D和MC10EP35DG的区别 |