MPC565MZP56

NXP  MPC565MZP56  微控制器, 32位, AEC-Q100, 电源架构, 56 MHz, 1 MB, 36 KB, 388 引脚, BGA

The is a 32-bit Microcontroller a member of the MPC500 family of microprocessors that implements the power architecture instruction standard architecture. The MPC565 is integrated with a floating point unit, an advanced peripheral set and 1MB of flash memory on a single chip. The device incorporates 36kB internal RAM, 40-channel 10-bit A/D converter, Three TouCAN modules TouCAN A, TouCAN B, TouCAN C and 56 general-purpose I/O pins.

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An MPC500 core with a floating point unit FPU and a burst buffer controller BBC

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Unified system integration unit USIU

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Flexible memory controller

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Enhanced interrupt controller

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3 Time processor units TPU3

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22 Timer channel modular I/O system MIOS14

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2 Enhanced queued analog to digital converters QADC64E A, QADC64E B

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2 Queued serial multi-channel modules QSMCM A, QSMCM B

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Queued serial peripheral interface QSPI

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2 Serial controller interfaces SCI/UART

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J1850 DLCMD2 communications module

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Nexus debug port class 3 - IEEE-ISTO 5001-1999

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JTAG and background debug mode BDM

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40MHz Operation 56MHz operation is optional