MC10E1652

与LATCH双ECL输出比较器 DUAL ECL OUTPUT COMPARATOR WITH LATCH

The comparator is fabricated using "s advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is available in both a 16-pin DIP and a 20-pin surface mount package. However, the MC10E1652 provides user programmable hysteresis. The latch enable LENabar and LENbbar input pins operate from standard ECL 10H logic levels. When the latch enable is at a logic high level, the MC10E1652 acts as a comparator; hence, Q will be at a logic high level if V1 > V2 V1 is more positive than V2. Qbar is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state, providing the latch enable setup and hold time constraints are met. The level of input hysteresis is controlled by applying a bias voltage to the HYS pin. The 100 Series contains temperature compensation.

Features

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Typical 3.0 dB Bandwidth > 1.0 GHz

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Typical V to Q Propagation Delay of 775 ps

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Typical Output Rise/Fall of 350 ps

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Common Mode Range -2.0 V to +3.0 V

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Individual Latch Enables

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Differential Outputs

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Operating Mode: VCC = 5.0 V, VEE = -5.2 V

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Programmable Input Hysteresis

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No Internal Input Pulldown Resistors

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ESD Protection: > 2 KV HBM, > 100 V MM

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Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

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Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

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Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34

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Transistor Count = 85 devices