八路D触发器与时钟使能 OCTAL D FLIP-FLOP WITH CLOCK ENABLE
The /74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable CE is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop"s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
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