MC100EPT21DR2

3.3V差分LVPECL / LVDS / CML到LVTTL / LVCMOS翻译 3.3V Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL Positive ECL, LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only +3.3 V and ground are required. The small outline 8−lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.

The VBB output allows this EPT21 to be cap coupled in either single−ended or differential input mode. When single−ended cap coupled, VBB output is tied to the D input and D is driven for a non−inverting buffer, or VBB output is tied to the D input and D is driven for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 μF capacitor. For additional information see AND8020/D. For a single−ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single−ended direct connection or port to another device.

Features

• 1.4 ns Typical Propagation Delay

• Maximum Frequency > 275 MHz Typical

• LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs

• 24 mA TTL outputs

• Operating Range: VCC = 3.0 V to 3.6 V with GND = 0 V

• The 100 Series Contains Temperature Compensation

• VBB Output

• Pb−Free Packages are Available