双D触发器具有置位和复位 Dual D Flip-Flop with Set and Reset
High−Performance Silicon−Gate CMOS
The is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Qoutputs are available from each flip−flop. The Set and Reset inputs are asynchronous.
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 A
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7.0 A Requirements
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant