








Clock Multiplexer 20Out 2IN 1:20 52Pin QFN EP Tray
The NB100LVEP221 is a low skew 2:1:20 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1bar can also receive HSTL signal levels. The LVPECL input signals can be either differential or single-ended if the VThe LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open unterminated without affecting skew.The NB100LVEP221, as with most other ECL devices, can be operated from a positive V supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D. pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to V as a switching reference voltage. V may also rebias AC coupled inputs. When used, decouple V via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VSingle-ended CLK input operation is limited to V >/= 3.0 V in LVPECL mode, or V
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| 型号/品牌 | 代替类型 | 替代型号对比 |
|---|---|---|
NB100LVEP221MNG ON Semiconductor 安森美 | 当前型号 | 当前型号 |
PI49FCT32805QEX 美台 | 功能相似 | NB100LVEP221MNG和PI49FCT32805QEX的区别 |
PI49FCT32805QE 美台 | 功能相似 | NB100LVEP221MNG和PI49FCT32805QE的区别 |
PI49FCT32805Q 美台 | 功能相似 | NB100LVEP221MNG和PI49FCT32805Q的区别 |