OMAPL137DZKBT3

C6747 DSP+Arm 处理器 256-BGA -40 to 125

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs.

The OMAP-L137 device enables original-equipment manufacturers OEMs and original-design manufacturers ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer RISC technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 CP15, protection module, and data and program Memory Management Units MMUs with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag VIVT. The ARM core also has 8KB of RAM Vector Table and 64KB of ROM.

The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache L1P is a 32-KB direct mapped cache and the Level 1 data cache L1D is a 32-KB 2-way set-associative cache. The Level 2 program cache L2P consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC EMAC with a management data input/output MDIO module; two I2C Bus interfaces; 3 multichannel audio serial ports McASPs with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable one configurable as watchdog; a configurable 16-bit host-port interface HPI; up to 8 banks of 16 pins of general-purpose input/output GPIO with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces one with both RTS and CTS; three enhanced high-resolution pulse width modulator eHRPWM peripherals; three 32-bit enhanced capture eCAP module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator APWM outputs; two 32-bit enhanced quadrature encoded pulse eQEP peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface EMIFA for slower memories or peripherals, and a higher speed memory interface EMIFB for SDRAM.

The Ethernet Media Access Controller EMAC provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.