PCA9511ADP

可热插拔的I2C总线和SMBus总线缓冲器 Hot swappable I2C-bus and SMBus bus buffer

The is a hot swappable I²C-bus and SMBus Buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, this provides bidirectional buffering, keeping the backplane and card capacitances isolated. Its rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. It incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low current mode when asserted LOW and an open-drain READY output pin, which indicates that the backplane and card sides are connected together or not. During insertion, buffer SDA and SCL lines are pre-charged to 1V to minimize the current required to charge the parasitic capacitance of the chip.

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Compatible with I²C-bus Standard-mode, I²C-bus Fast-mode and SMBus standards

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Active HIGH ENABLE input

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Active HIGH READY open-drain output

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Supporting clock stretching and multiple master arbitration/synchronization

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Built-in ∆V/∆t rise time accelerators

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Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100mA

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0Hz to 400kHz Clock frequency