P3P623S00EG-16TR

P3P623S00EG-16TR图片1
P3P623S00EG-16TR图片2
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P3P623S00EG-16TR概述

Zero Delay PLL Clock Buffer Single 16Pin TSSOP T/R

P3P623S00B/E is a versatile, 3.3V zero-dealy buffer designed to distribute Timing-Safe™ clocks with peak EMI reduction.P3P623S00B is an eight pin version, accepts one reference input and drives out one low skew Timing-Safe™ clock.P3P623S00E accepts one reference input and drives out eight low-skew Timing-Safe™clocks.P3P623S0B/E has an SS% that selects two different deviation and associated Input-Output skewTskew.P3P623S00E has a CLKOUT for adjusting the Input-Output clock dealy, depending upon the value of capacitor connected at this pin to GND.P3P623S00B/E operates from a 3.3V supply and is available in two different packages, as shown in the ordering information table.

Features

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Clock distribution with Timing-Safe Peak EMI Reduction
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2 different Spread Selection options
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Spread Spectrum can be turned ON/OFF
P3P623S00EG-16TR中文资料参数规格
技术参数

无卤素状态 Halogen Free

输出接口数 1

电路数 1

输入数 1

最大占空比 60 %

下降时间Max 2.5 ns

上升时间Max 2.5 ns

电源电压 3V ~ 3.6V

封装参数

安装方式 Surface Mount

引脚数 16

封装 TSSOP-16

外形尺寸

高度 0.95 mm

封装 TSSOP-16

物理参数

工作温度 0℃ ~ 70℃

其他

产品生命周期 Active

包装方式 Tape & Reel TR

制造应用 Displays and memory interface systems.

符合标准

RoHS标准 RoHS Compliant

含铅标准 Lead Free

数据手册

P3P623S00EG-16TR引脚图与封装图
P3P623S00EG-16TR引脚图
P3P623S00EG-16TR封装图
P3P623S00EG-16TR封装焊盘图
在线购买P3P623S00EG-16TR
型号: P3P623S00EG-16TR
描述:Zero Delay PLL Clock Buffer Single 16Pin TSSOP T/R

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