PKD01EY

单片峰值检波器与复位和保持模式 Monolithic Peak Detector with Reset-and-Hold Mode

GENERAL DESCRIPTION

The PKD01 tracks an analog input signal until a maximum amplitude is reached. The maximum value is then retained as a peak voltage on a hold capacitor. Being a monolithic circuit, the PKD01 offers significant performance and package density advantages over hybrid modules and discrete designs without sacrificing system versatility. The matching characteristics attained in a monolithic circuit provide inherent advantages when charge injection and droop rate error reduction are primary goals.

FEATURES

Monolithic Design for Reliability and Low Cost

High Slew Rate: 0.5 V/μs

Low Droop Rate

   TA = 25°C: 0.1 mV/ms

   TA = 125°C: 10 mV/ms

Low Zero-Scale Error: 4 mV

Digitally Selected Hold and Reset Modes

Reset to Positive or Negative Voltage Levels

Logic Signals TTL and CMOS Compatible

Uncommitted Comparator On-Chip

Available in Die Form