NXP PCA9665PW 专用接口, I2C, 并行, SMBus, I2C总线与SMBus系统应用, 2.3 V, 3.6 V, TSSOP, 20 引脚
The is an Interface between most standard parallel-bus microcontrollers/microprocessors and the serial I²C-bus and allows the parallel bus system to communicate bidirectionally with the I²C-bus. It can operate as a master or a slave and can be a transmitter or receiver. Communication with the I²C-bus is carried out on a byte or buffered mode using interrupt or polled handshake. It controls all the I²C-bus specific sequences, protocol, arbitration and timing with no external timing element required. It contains eleven registers which are used to configure the operation of the device as well as to send and receive serial data. There are four registers that can be accessed directly and seven registers that are accessed indirectly by setting a register pointer. The four direct registers are selected by setting pins A0 and A1 to the appropriate logic levels before a read or write operation is executed on the parallel bus.
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- Both master and slave functions
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- Multi-master capability
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- Internal oscillator trimmed to 15% accuracy reduces external components
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- I²C-bus General call capability
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- Software reset on parallel bus
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- Standard-mode and fast-mode I²C-bus capable and compatible with SMBus
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- Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA
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- Software reset on the parallel bus
