微处理器 - MPU P4081 R3 NO ENC 1000 MHZ
Overview
The P4080 was the flagship product for the QorIQ® family when it was first introduced to the market. It provided the foundation upon which the P5, P3, P2 and P1 processor families were built. In addition to those families, P4080 expanded its portfolio with the P4040 and P4081. These processors provide a performance, power and price to meet a broad spectrum of high-performance applications. It combines four to eight Power Architecture® e500mc cores—operating at frequencies up to 1.5 GHz—with high-performance data path acceleration logic and network and peripheral bus interfaces designed for 45 nm technology to deliver high-performance, next-generation networking services in a very low-power envelope.
The QorIQ P4080 processor can be used for combined control, data path and application layer processing. Its high level of integration offers significant performance benefits compared to multiple discrete devices while greatly simplifying board design. The processor is well-suited for applications that are highly compute-intensive, I/O intensive or both, making it ideal for applications such as enterprise and service provider routers, switches, base station controllers, radio network controllers RNCs, long term evolution LTE and general-purpose embedded computing systems in the networking, telecom/datacom, wireless infrastructure, military and aerospace markets.
Product P4081NSE7KKC on this page is Not Recommended for New Designs.
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## Features
### Core Complex
* Four to eight high-performance e500mc cores up to 1.5 GHz
* Three-level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 2 MB shared L3
* Hardware hypervisor for safe partitioning of operating systems between cores
### Networking Elements
* High-speed peripheral interfaces
* Three PCI Express® v2.0 controllers/ports running at up to 5 GHz
* Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz
### Accelerators and Memory Control
* Dual 64-bit 72-bit with ECC DDR2/3 memory controllers up to 1.3 GHz data rate
* DPAA incorporating acceleration for the following functions
* Packet parsing, classification, and distribution
* Queue management for scheduling, packet sequencing, and congestion management
* Hardware buffer management for buffer allocation and de-allocation
* Encryption SEC 4.0
* RegEx Pattern Matching PME 2.0
* Ethernet interfaces
* Two 10 GBps Ethernet XAUI controllers
* Eight 1 GBps Ethernet SGMII controllers
### Basic Peripherals and Interconnect
* SD/MMC,
* Two dual UARTs DUART,
* Four I²C,
* Two USB 2.0 with integrated PHY
* Enhanced local bus controller eLBC
* Serial peripheral interface SPI controller, four I²C controllers, two dual UARTs DUART,
* Multicore programmable interrupt controller PIC
* Two 4-channel DMA engines
### Additional Features
* Trusted boot capability to ensure only the correct code is booted and that code is not reverse-engineered
* Pin-and software-compatible with P3041, P4040, P5010 and P5020
* This product is included in "s product longevity program, with assured supply for a minimum of 10 years after launchComparison Table
### Core Complex
* Four to eight high-performance e500mc cores up to 1.5 GHz
* Three-level cache-hierarchy: 32 KB I/D L1, 128 KB private L2 per core, 2 MB shared L3
* Hardware hypervisor for safe partitioning of operating systems between cores
### Networking Elements
* High-speed peripheral interfaces
* Three PCI Express® v2.0 controllers/ports running at up to 5 GHz
* Two Serial RapidIO® 1.2 controllers/ports running at up to 3.125 GHz
### Accelerators and Memory Control
* Dual 64-bit 72-bit with ECC DDR2/3 memory controllers up to 1.3 GHz data rate
* DPAA incorporating acceleration for the following functions
* Packet parsing, classification, and distribution
* Queue management for scheduling, packet sequencing, and congestion management
* Hardware buffer management for buffer allocation and de-allocation
* Encryption SEC 4.0
* RegEx Pattern Matching PME 2.0
* Ethernet interfaces
* Two 10 GBps Ethernet XAUI controllers
* Eight 1 GBps Ethernet SGMII controllers
### Basic Peripherals and Interconnect
* SD/MMC,
* Two dual UARTs DUART,
* Four I²C,
* Two USB 2.0 with integrated PHY
* Enhanced local bus controller eLBC
* Serial peripheral interface SPI controller, four I²C controllers, two dual UARTs DUART,
* Multicore programmable interrupt controller PIC
* Two 4-channel DMA engines
### Additional Features
* Trusted boot capability to ensure only the correct code is booted and that code is not reverse-engineered
* Pin-and software-compatible with P3041, P4040, P5010 and P5020
* This product is included in NXP"s product longevity program, with assured supply for a minimum of 10 years after launch