S25FL512SAGMFIG11

SPANSION  S25FL512SAGMFIG11  闪存, 或非, 512 Mbit, 133 MHz, SPI, SOIC, 16 引脚

The is a Flash Non-volatile Memory connects to a host system via a serial peripheral interface. Traditional SPI single bit serial input and output is supported as well as optional two bit and four bit serial commands. This multiple width interface is called SPI Multi-I/O or MIO. In addition, the FL-S family adds support for double data rate read commands for SIO, DIO and QIO that transfer address and read data on both edges of the clock. The eclipse architecture features a page programming buffer that allows up to 256 words to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

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SPI clock polarity and phase modes 0 and 3

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Common flash interface CFI data for configuration information

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Programming 1.5Mbytes/s

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Erase 0.5 to 0.65Mbytes/s

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100000 Program-erase cycles on any sector typical

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20-year Typical data retention