SN74LVC2G125YZPR

具有三态输出的双总线缓冲器门 DUAL BUS BUFFER GATE WITH 3 STATE OUTPUTS

The is a dual Bus Buffer Gate with 3-state outputs. The outputs are disabled when the associated output-enable OE input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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±24mA Output drive at 3.3V

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<0.8V at VCC = 3.3V typical VOLP Output ground bounce

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>2V at VCC = 3.3V Typical VOHV Output VOH undershoot

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Inputs from a Maximum of 5.5V down

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10µA Maximum ICC low power consumption

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Maximum tpd of 4.3ns at 3.3V

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Ioff supports live insertion, partial power down mode and back drive protection

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ESD protection exceeds JESD 22

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Latch-up performance exceeds 100mA per JESD 78, Class II