SN74ALVCH16501DL

18位通用总线收发器，具有三态输出 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.

Data flow in each direction is controlled by output-enable OEAB and OEBA\, latch-enable LEAB and LEBA, and clock CLKAB and CLKBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA\, LEBA, and CLKBA. The output enables are complementary OEAB is active high and OEBA\ is active low.

To ensure the high-impedance state during power up or power down, OEBA\ should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.