8位LVTTL至GTLP总线收发器 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed about three times faster than standard LVTTL or TTL backplane operation is a direct result of GTLP"s reduced output swing <1 V, reduced input threshold levels, improved differential input, OEC circuitry, and -OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 .
GTLP is the Texas Instruments TI derivative of the Gunning Transceiver Logic GTL JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP, but the user has the flexibility of using this device at either GTL VTT = 1.2 V and VREF = 0.8 V or GTLP VTT = 1.5 V and VREF = 1 V signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable OE\\\\ input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. View datasheet View product folder
电源电压DC 3.30 V, 3.45 V max
输出电流 50.0 mA
电路数 1
通道数 1
时钟频率 175MHz max
位数 8
电压波节 3.30 V
静态电流 20.0 mA
工作温度Max 85 ℃
工作温度Min -40 ℃
输出通道数 8
电源电压 3.15V ~ 3.45V
安装方式 Surface Mount
引脚数 24
封装 TVSOP-24
封装 TVSOP-24
工作温度 -40℃ ~ 85℃
产品生命周期 Active
包装方式 Tape & Reel TR
RoHS标准 RoHS Compliant
含铅标准 Lead Free
ECCN代码 EAR99
型号/品牌 | 代替类型 | 替代型号对比 |
---|---|---|
SN74GTLPH306DGVR TI 德州仪器 | 当前型号 | 当前型号 |
74GTLPH306DGVRE4 德州仪器 | 完全替代 | SN74GTLPH306DGVR和74GTLPH306DGVRE4的区别 |