SN74AS646DW

八路总线收发器和寄存器具有三态输出 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

description

These devices consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock CLKAB or CLKBA input. Figure 1

illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers.

Independent Registers for A and B Buses

Multiplexed Real-Time and Stored Data

Choice of True or Inverting Data Paths

Choice of 3-State or Open-Collector Outputs

Package Options Include Plastic Small-Outline DW Packages, Ceramic Chip Carriers FK, and Standard Plastic NT and Ceramic JT 300-mil DIPs