SPC570S50E1CEFAR

32位微控制器 - MCU 32-bit Power Architecture MCU for Automotive Chassis and Safety Applications

The 32-bit SPC570Sx automotive microcontrollers, ASIL-D compliant are a family of system-on-chip SoC devices designed to meet the challenges of the next generation of entry-level vehicle safety critical applications such as ABS and Airbag.

The SPC570Sx microcontrollers operate at speeds up to 80 MHz and offer high performance processing with low power consumption. They are compatible with the existing development infrastructure of current Power Architecture®devices and are supported with software drivers, operating systems and configuration code to assist with application development.

**Key Features**

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Features

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High performance e200z0h dual core

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32-bit Power Architecture technology CPU

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Core frequency as high as 80 MHz

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Single issue 4-stage pipeline in-order execution core

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Variable Length Encoding VLE

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Up to 544 KB 512 KB code + 32 KB data, suitable for EEPROM emulation on-chip flash memory: supports read during program and erase operations, and multiple blocks allowing EEPROM emulation

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Up to 48 KB on-chip general-purpose SRAM

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Multi-channel direct memory access controller eDMA with 16 channels

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Comprehensive new generation ASILD safety concept

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Safety of bus masters core+INTC, DMA by delayed lockstep approach

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Safety of storage Flash, SRAM by mainly ECC

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Safety of the data path to storage and periphery by mainly End-to-End EDC E2E EDC

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Clock and power, generation and distribution, supervised by dedicated monitors

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Fault Collection and Control Unit FCCU for collection and reacRev 3tion to failure notifications

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Memory Error Management Unit MEMU for collection and reporting of error events in memories

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Boot time MBIST and LBIST for latent faults

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Check of safety mechanisms availability and error reaction path functionality by dedicated mechanisms

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Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST

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Safety of the periphery by application-level measures supported by replicated peripheral bridges and by LBIST

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Further measures on dedicated peripherals e.g. ADC supervisor

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Junction temperature sensor

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8-region system memory protection unit SMPU with process ID support tasks isolation

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Enhanced SW watchdog

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Cyclic redundancy check CRC unit

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Dual phase-locked loops with stable clock domain for peripherals and FM modulation domain for computational shell

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Nexus Class 3 debug and trace interface

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Communication interfaces

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2 LINFlexD modules

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3 deserial serial peripheral interface DSPI modules

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Up to 2 FlexCAN interfaces with 32 message buffers each

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On-chip CAN/UART Bootstrap loader with Boot Assisted Flash BAF. Physical Interface PHY can be

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UART

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CAN

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Two enhanced 12-bit SAR analog converters

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1.5 μs conversion time

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16 physical channels fully shared between the 2 SARADC units

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Supervisor ADC concept

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Programmable Cross Triggering Unit CTU

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Single 3.3 V or 5V voltage supply

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4 general purpose eTimer units 6 channels each

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Junction temperature range –40 °C to 150 °C