SN65LV1224BRHBT

TEXAS INSTRUMENTS  SN65LV1224BRHBT  SerDes, 解串器, 660 Mbps, LVDS, LVTTL, QFN, 32 引脚

The is a 10-bit deserializer SerDes Transmitter designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 to 66MHz. Including overhead, this translates into a serial data rate between 120 and 792Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

.

Pin-compatible superset of DS92LV1023/DS92LV1224

.

Synchronization mode for faster lock

.

Lock indicator

.

No external components required for PLL

.

Programmable edge trigger on clock

.

Flow-through pin-out for easy PCB layout

.

<450mW at 66MHz Typical power consumption

.

Green product and no Sb/Br