SN65LVDS117DGGR

双路 8 端口 LVDS 中继器 64-TSSOP -40 to 85

The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four "109 or eight "117 differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.

The line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling LVDS. LVDS, as specified in EIA/A-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

The intended application of these devices, and the LVDS signaling technique, is for point-to-point or point-to-multipoint distributed simplex baseband data transmission on controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock and data distribution trees.

The SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.