SN74ALS137AN

TEXAS INSTRUMENTS  SN74ALS137AN  逻辑芯片, 译码器/信号分离器, 3至8线, 16DIP

description

The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/demultiplexers with latches on the three address inputs. When the latch-enable LE input is low, the devices act as decoders/demultiplexers. When LE goes from low to high, the address present at the select A, B, and C inputs is stored in the latches. Further address changes are ignored as long as LE remains high. The output-enable controls G1 and G2 control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2 is high. These devices are ideally suited for implementing glitch-free decoders in strobed stored-address applications in bus-oriented systems.

• Combines Decoder and 3-Bit Address Latch

• Incorporates Two Output Enables to Simplify Cascading

• Package Options Include Plastic Small Outline D Packages, Ceramic Chip Carriers FK, and Standard Plastic N and Ceramic J 300-mil DIPs