SN74AHC138DRG4

3 线至 8 线解码器/多路解复用器 16-SOIC -40 to 85

description

The ’AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

Operating Range 2-V to 5.5-V VCC

Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems

Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception

Latch-Up Performance Exceeds 250 mA Per JESD 17

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model A114-A

– 200-V Machine Model A115-A

– 1000-V Charged-Device Model C101