SN74AUP1G32DSF2

逻辑门 Low-Pwr Sgl 2-Input Pos-OR Gate

DESCRIPON/ORDERING INFORMATION

The AUP family is TI"s premier solution to the industry"s low-power needs in battery-powered portable

applications. This family ensures a very low static and dynamic power consumption across the entire VCC

range of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity see Figure 1 and Figure 2.

FEATURES

• Available in the Texas Instruments NanoStar™ Package

• Low Static-Power Consumption ICC = 0.9 mA Max

• Low Dynamic-Power Consumption Cpd = 4.3 pF Typ at 3.3 V

• Low Input Capacitance CI = 1.5 pF Typ

• Low Noise – Overshoot and Undershoot <10% of VCC

• Ioff Supports Partial-Power-Down Mode Operation

• Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at the Input Vhys = 250 mV Typ at 3.3 V

• Wide Operating VCC Range of 0.8 V to 3.6 V

• Optimized for 3.3-V Operation

• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation

• tpd = 4.6 ns Max at 3.3 V

• Suitable for Point-to-Point Applications

• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

• ESD Performance Tested Per JESD 22

  – 2000-V Human-Body Model A114-B, Class II

  – 1000-V Charged-Device Model C101