SN74AUP1G126DRLR

低功耗单路总线缓冲器，具有3 - STATS输出门 LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATS OUTPUT

The AUP family is ’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity see Figure 1 and Figure 2.

This bus buffer gate is a single line driver with a 3-state output. The output is disabled when the output-enable OE input is low. This device has the input-disable feature, which allows floating input signals.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.