SN74LVC2G241DCUT

双缓冲/驱动器，具有三态输出 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS

The is a dual Buffer/Line Driver designed for 1.65 to 5.5V VCC operation. This device is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers and bus-oriented receivers and transmitters. This device is organized as two 1-bit line drivers with separate output-enable 1OE, 2OE inputs. When 1OE is low and 2OE is high, the device passes data from the A inputs to the Y outputs. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and OE should be tied to GND through a pull-down resistor and the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

.

IOFF Supports live insertion, partial-power-down mode and back-drive protection

.

Can be used as a down translator to translate inputs from 5.5V down to the VCC level

.

Latch-up performance exceeds 250mA per JESD 17

.

Inputs accept voltages to 5.5V

.

4.1ns at 3.3V Propagation delay tpd

.

10µA ICC Low power consumption

.

±24mA Output drive at 3.3 V

.

<0.8V at VCC = 3.3V, TA = 25°C VOLP output ground bounce

.

>2V at VCC = 3.3V, TA = 25°C VOHV output VOH undershoot

.

Green product and no Sb/Br