SN74AHC573DWRG4

具有三态输出的八路透明 D 型锁存器 20-SOIC -40 to 125

description/ordering information

The ’AHC573 devices are octal transparent D-type latches designed for 2-V to 5.5-V VCC operation. When the latch-enable LE input is high, the Q outputs follow the data D inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable OE input can be used to place the eight outputs in either a normal logic state high or low or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OEdoes not affect the internal operations of the latches. Old data can be retained or new data can

be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Operating Range 2-V to 5.5-V VCC

3-State Outputs Directly Drive Bus Lines

Latch-Up Performance Exceeds 250 mA Per JESD 17