SN74F175NSR

翻两番D型触发器与Clear QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR

This positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear CLR\ input. Information at the data D inputs meeting setup-time requirements is transferred to outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock CLK input is at either the high or low level, the D-input signal has no effect at the output.