SN74LV8154N

TEXAS INSTRUMENTS  SN74LV8154N  芯片, 逻辑电路 - 二进制计数器

The is a 16-bit dual Binary Counter with 3-state output registers. It is designed for 2 to 5.5V VCC operation. It has dedicated clock inputs. The counter shares a clocked storage register to sample and save the counter contents. Both counters share an asynchronous clear input. The 32-bit storage register can be mapped on the output bus 8-bits at a time. Four bus reads are needed to access the contents of both stored counts. The two counters can be chained by connecting CLKBEN\ to RCOA\\. All clocks are positive edge triggered. All other inputs are active low. It is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Can be used as two 16-bit counters or a single 32-bit counter

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Ioff Supports partial-power-down mode operation

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Latch-up performance exceeds 250mA per JESD 17

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8-bit Counter read bus