SN74ABT543NT

Bus XCVR Single 8CH 3-ST 24Pin PDIP

description

The ′ABT543 octal transceivers contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable LEAB or LEBA and output-enable OEAB or OEBA inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable CEAB input must be low in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA, LEBA, and OEBA inputs.

• State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation

• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model C = 200 pF, R = 0

• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17

• Typical VOLP Output Ground Bounce

   < 1 V at VCC = 5 V, TA = 25°C

• High-Drive Outputs −32-mA IOH, 64-mA IOL

• Package Options Include Plastic Small-Outline DW and Shrink Small-Outline DB Packages, Ceramic Chip Carriers FK, and Plastic NT and Ceramic JT DIPs