S25FL127SABMFV101

闪存, MirrorBit架构, 串行NOR, 128 Mbit, 16M x 8位, SPI, SOIC, 8 引脚

The Cypress S25FL127S device is a flash non-volatile memory product using: - MirrorBit technology that stores two data bits in each memory array transistor - Eclipse architecture that dramatically improves program and erase performance - 65 nm process lithography This device connects to a host system via a Serial Peripheral Interface SPI. Traditional SPI single bit serial input and output Single I/O or SIO is supported as well as optional two bit Dual I/O or DIO and four bit Quad I/O or QIO serial commands. This multiple width interface is called SPI Multi-I/O or MIO. The Eclipse architecture features a Page Programming Buffer that allows up to 128 words 256 bytes or 256 words 512 bytes to be programmed in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms.

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CMOS 3.0 Volt core

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128 Mbits 16 Mbytes

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Serial peripheral interface SPI with multi-I/O

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100,000 program-erase cycles per sector, minimum

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One Time Program OTP array of 1024 bytes

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Cypress 65 nm MirrorBit Technology with Eclipse architecture